Dynamic packet size control for MPEG-4 data partition mode

ABSTRACT

A dynamic AC prediction technique is implemented in a data partition mode which automatically disables AC prediction for encoding the current macroblock in the next packet when packet overflow occurs. Otherwise, when there is no overflow, AC prediction remains enabled to maintain compression efficiency. More particularly, in the preferred embodiment, a determination is first made whether a macroblock causes a packet overflow if it is encoded in the current packet. If so, a new packet is initiated into which the macroblock is encoded without AC prediction as the first macroblock. Otherwise, the macroblock with AC prediction remains in the current packet and a new macroblock is encoded.

RELATED APPLICATIONS

The present application is a divisional of and claims the benefit ofU.S. patent application Ser. No. 10/721,709, filed Nov. 25, 2003,entitled “DYNAMIC PACKET SIZE CONTROL FOR MPEG-4 DATA PARTITION MODE,”naming Ram Prabhakar, Harikrishna M. Reddy, Lefan Zhong, Wei Sun,Leonardo Vainsencher, and Visalakshi Vaduganathan as inventors, assignedto the assignee of the present invention, and having attorney docketnumber NVID-P000899. That application is incorporated herein byreference in its entirety and for all purposes.

The present application is related to U.S. patent application Ser. No.______,filed Dec. ______, 2007, entitled “DYNAMIC PACKET SIZE CONTROLFOR MPEG-4 DATA PARTITION MODE,” naming Ram Prabhakar, Harikrishna M.Reddy, Lefan Zhong, Wei Sun, Leonardo Vainsencher, and VisalakshiVaduganathan as inventors, assigned to the assignee of the presentinvention, and having attorney docket number NVID-P000899.D2. Thatapplication is incorporated herein by reference in its entirety and forall purposes.

FIELD OF THE INVENTION

The invention generally relates to computer systems, and moreparticularly relates to dynamic packet size control in MPEG-4 datapartition mode.

BACKGROUND OF THE INVENTION

Moving Pictures Experts Groups (MPEG) is an International StandardsOrganization (ISO) standard for compressing video data. Videocompression is important in making video data files, such as full-lengthmovies, more manageable for storage (e.g., in optical storage media),processing, and transmission. In general, MPEG compression is achievedby eliminating redundant and irrelevant information. Because videoimages typically consist of smooth regions of color across the screen,video information generally varies little in space and time. As such, asignificant part of the video information in an image is predictable andtherefore redundant. Hence, a first objective in MPEG compression is toremove the redundant information and leaving only the true orunpredictable information. On the other hand, irrelevant video imageinformation is information that cannot be seen by the human eye undercertain reasonable viewing conditions. For example, the human eye isless perceptive to noise at high spatial frequencies than noise at lowspatial frequencies and less perceptive to loss of details immediatelybefore and after a scene change. Accordingly, the second objective inMPEG compression is to remove irrelevant information. The combination ofredundant information removal and irrelevant information removal allowsfor highly compressed video data files.

MPEG compression incorporates various well-known techniques to achievethe above objectives including: motion-compensated prediction, DiscreteCosine Transform (DCT), quantization, and Variable-Length Coding (VLC).DCT is an algorithm that converts pixel data into sets of spatialfrequencies with associated coefficients. Due to the non-uniformdistribution of the DCT coefficients wherein most of the non-zero DCTcoefficients of an image tend to be located in a general area, VLC isused to exploit this distribution characteristic to identify non-zeroDCT coefficients from zero DCT coefficients. In so doing,redundant/predictable information can be removed. Additionally, havingdecomposed the video image into spatial frequencies under DCT means thathigher frequencies via their associated DCT coefficients can be codedwith less precision than the lower frequencies via their associated DCTcoefficients thereby allowing irrelevant information to be removed.Hence, quantization may be generalized as a step to weight the DCTcoefficients based on the amount of noise that the human eye cantolerate at each spatial frequency so that a reduced set of coefficientscan be generated.

Additionally, MPEG compression also includes additional compressionstages such as Alternative Coefficient/Discrete Coefficient (AC/DC)prediction. AC is typically defined as a DCT coefficient for which thefrequency in one or both dimensions is non-zero (higher frequency). DCis typically defined as a DCT coefficient for which the frequency iszero (low frequency) in both dimensions. An AC/DC prediction modulepredicts the AC and DC for the current block based on AC and DC valuesof adjacent blocks such as an adjacent left top block, a top block, andan adjacent left block. For example, the prediction can be made asfollows:

If (|B−A|≧|B−C) then X=A

-   -   else X=C        where B is the AC or DC value of the left top block relative to        the current block, C is the AC or DC value of the top block        relative to the current block, A is the AC or DC value of the        left block relative to the current block, and X is the AC or DC        value of the current block.

Such predictions and other features are described in “MPEG-4 InformationTechnology-Coding of Audio-Visual Objects-Part 2: Visual”ISO/IEC/14496-2:1999 which is herein incorporated by reference in itsentirety. Additionally, U.S. Pat. No. 6,341,144 and its continuationU.S. Pat. No. 6,556,625 describes in detail AC/DC predictions and areherein incorporated by reference in their entirety.

Compressed video data is vulnerable to transmission errors. MPEG-4offers error resilience tools to localize the effects of errors,re-establish synchronization, and recover erroneous data. The end resultis more reliable data transmission. These tools include data partition,packetization, and reversible VLC. Data partitioning is designed tolocalize and isolate the effects of errors by separating andpartitioning motion and shape data from texture data in a video packet.A video packet is made up of one or several macroblocks. A frame (a.k.a.Video Object Plane in MPEG-4 terminology) consists of several packets.Each packet starts with markers and the packet header. The data in eachpacket are encoded independently relative to other packets. Datapartition mode in MPEG-4 requires data in any packet to be divided intothree parts. Each part consists of bitstream components from allmacroblocks in the packet. During data partition mode, a packet size(i.e., the number of data bits in the packet) is limited to 2048 bitsfor simple profile level-1 video bitstream, 4096 bits for simple profilelevel-2 video bitstream, and 8192 bits for simple profile level-3 videobitstream.

As a result of the strict packet sizes in data partition mode, there areinherent concerns about packet data overflow during the encoding of amacroblock. To prevent the data loss associated with packet overflow, amacroblock which causes the overflow needs to be re-encoded in a newpacket. However, if the AC prediction is always turned on during datapartition mode, such re-encoding may cause a change in the AC predictiondirection and predicted differences which in turn effects the ZigZag runlength of the bitstream. Conversely, if the AC prediction is turned offcompletely during data partition mode, the compression efficiency isnegatively impacted.

Thus, a need exists for a method and apparatus to prevent video packetoverflow in a MPEG data partition mode while minimizing the compressionefficiency impact and maintaining the video quality.

SUMMARY OF THE INVENTION

Accordingly, the present invention provides a method and apparatus toprevent video packet overflow in a MPEG data partition mode whileminimizing the compression efficiency impact and maintaining videoquality.

The present invention meets the above need with a dynamic AC predictiontechnique for a data partition mode. In according to the presentinvention, the dynamic AC prediction technique first determines whethera macroblock causes a packet overflow if it is encoded in the currentpacket. If so, a new packet is initiated into which the macroblock isencoded without AC prediction as the first macroblock. Otherwise, themacroblock with AC prediction remains in the current packet and a newmacroblock is encoded.

All the features and advantages of the present invention will becomeapparent from the following detailed description of its preferredembodiments whose description should be taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates, for example, a high-level diagram of a computingdevice 100 which implements the present invention.

FIG. 2 illustrates in greater detail graphics/display controller 107 ofthe computing device 100.

FIG. 3 illustrates the relevant components of an embodiment of MPEGencoder 213 which implements the present invention.

FIG. 4 illustrates a format structure of adjacent DCT coefficient blocksto be processed by AC/DC prediction module 312 which implements thepresent invention.

FIG. 5 illustrates the relevant components of an exemplary embodiment ofAC/DC prediction module 312 which implements the present invention.

FIG. 6 is a flow chart illustrating an embodiment of the dynamic ACprediction method in accordance to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the present invention, numerousspecific details are set forth in order to provide a thoroughunderstanding of the present invention. However, it will be obvious toone skilled in the art that the present invention may be practicedwithout these specific details. In other instances well known methods,procedures, components, and circuits have not been described in detailas not to unnecessarily obscure aspects of the present invention. Whilethe following detailed description of the present invention is relatedto MPEG compressed video image data, it is to be appreciated that thepresent invention is also applicable to other data compression schemesinvolving video, audio, text, software, and other types of data.

In accordance to the present invention, a dynamic AC predictiontechnique is implemented for a data partition mode which automaticallydisables AC prediction for encoding the current macroblock in the nextpacket when packet overflow occurs. Otherwise, when there is nooverflow, AC prediction remains enabled to maintain compressionefficiency. More particularly, in the preferred embodiment, adetermination is first made whether a macroblock causes a packetoverflow if it is encoded in the current packet. If so, a new packet isinitiated into which the macroblock is encoded without AC prediction asthe first macroblock. Otherwise, the macroblock with AC predictionremains in the current packet and a new macroblock is encoded. Althoughno AC prediction is performed for a macroblock during re-encoding into anew packet, no quality degradation occurs in the new packet because, asthe first macroblock of a new packet, the macroblock is not likely tohave high correlation with macroblocks from the previous packet hence noAC prediction is likely needed and carried out for the first macroblock.However, AC prediction is performed for the subsequent macroblocks inthe new packet relative to this first macroblock. The above factorscontribute to improve video quality.

Reference is now made to FIG. 1 illustrates, as an example, a high-leveldiagram of computer system 100 in which the present invention may beimplemented or practiced. More particularly, computer system 100 may bea laptop or hand-held computer system. It is to be appreciated thatcomputer system 100 is exemplary only and that the present invention canoperate within a number of different computer systems including desktopcomputer systems, general-purpose computer systems, embedded computersystems, and others.

As shown in FIG. 1, computer system 100 is a highly integrated systemwhich includes of integrated processor circuit 101, peripheralcontroller 102, read-only-memory (ROM) 103, and random access memory(RAM) 104. The highly integrated architecture allows power to beconserved. Peripheral controller 102 is optional if there is a need tointerface with complex and/or high pin-count peripherals that are notprovided in integrated processor circuit 101.

While peripheral controller 102 is connected to integrated processorcircuit 101 on one end, ROM 103 and RAM 104 are connected to integratedprocessor circuit 101 on the other end. Integrated processor circuit 101comprises a processing unit 105, memory interface 106, graphics/displaycontroller 107, direct memory access (DMA) controller 108, and corelogic functions including encoder/decoder (CODEC) interface 109,parallel interface 110, serial interface 111, and input device interface112. Processing unit 105 integrates a central processing unit (CPU), amemory management unit (MMU), together with instruction/data caches.

CODEC interface 109 provides the interface for an audio source and/ormodem to connect to integrated processor circuit 101. Parallel interface110 allows parallel input/output (I/O) devices such as hard disks,printers, etc. to connect to integrated processor circuit 101. Serialinterface 111 provides the interface for serial I/O devices such asUniversal Asynchronous Receiver Transmitter (UART), Universal Serial Bus(USB), and Firewire (IEEE 1394) to connect to integrated processorcircuit 101. Input device interface 112 provides the interface for inputdevices such as keyboard, mouse, and touch pad to connect to integratedprocessor circuit 101.

DMA controller 108 accesses data stored in RAM 104 via memory interface106 and provides the data to peripheral devices connected to CODECinterface 109, parallel interface 110, serial interface 111, or inputdevice interface 112. DMA controller 108 also sends data from CODECinterface 109, parallel interface 110, serial interface 111, and inputdevice interface 112 to RAM 104 via memory interface 106.Graphics/display controller 107 requests and accesses the video/graphicsdata from RAM 104 via memory interface 106. Graphics/display controller107 then processes the data, formats the processed data, and sends theformatted data to a display device such as a liquid crystal display(LCD), a cathode ray tube (CRT), or a television (TV) monitor. Incomputer system 100, a single memory bus is used to connect integratedprocessor circuit 101 to ROM 103 and RAM 104.

The present invention is implemented as part of graphics/displaycontroller 107. Reference is now made to FIG. 2 illustrating in greaterdetail graphics/display controller 107. In general, graphics/displaycontroller 107 comprises CPU Interface Unit (CIF) 201, SRAM 202, PhaseLock Loop (PLL) circuit 203, oscillator 204, pixel processing logic 208,Graphics Engine (GE) 206, Memory Interface Unit (MIU) 207, Flat PanelInterface (FPI) 209, CRT Digital-to-Analog Converter (DAC) 210,post-processing module 211, MPEG-4 video decoder 212, and MPEG-4 videoencoder 213. Graphics/display controller 107 further includes a videoinput port to accommodate a video camera or any other input video signalincluding playback of a stored video input whether analog or digital.CIF 201 provides the interface to processing unit 105 and DMA controller108. Accordingly, CIF 201 routes requests and video/image data receivedfrom processing unit 105 to the desired destination. In particular, CIF201 sends register read/write requests and memory read/write requestsfrom the host CPU processing unit 105 and DMA controller 108 to theappropriate modules in graphics/display controller 107. For example,memory read/write requests are passed on to MIU 207 which in turnreads/writes the data from/to the frame buffer in SRAM 202. CIF 201 alsoserves as the liaison with DMA controller 108 to fetch data from systemmemory (ROM 103 and RAM 104) and provides the data to GE 206 and MIU207. Further, CIF 201 has a number of control registers which can beprogrammed by the host CPU in processing unit 105 to control the MPEGpost-processing process (e.g., the content of some of the controlregisters may be used to configure MPEG-4 decoder 212). CIF 201 alsopasses compressed video/image bitstream, including encoded video signalswith dynamic AC prediction as taught in accordance with the presentinvention, to MPEG-4 decoder 212 to perform imageconstruction/decompression. CIF 201 further passes uncompressedvideo/image bitstream received from a source connected to codecinterface 109 or serial interface 111 to MPEG-4 encoder to performcompression before the compressed bitstream can be transmitted to adevice connected directly or remotely to integrated processor circuit101.

The frame buffer in SRAM 202 is used to store the pixmap (i.e., a pixelpattern mapped into the frame buffer) of the image to be displayed onthe monitor as well to act as a temporary buffer for various purposes.Additionally, SRAM 202 may have memory allocated for video buffers andtransactional registers. GE 206 processes graphics/video image datawhich is then stored in the buffer in SRAM 202 based on commands issuedby the host CPU. GE 206 performs graphics operations (e.g., BitBLTs andROPs, area fills, line drawing) and provides hardware support forclipping, transparency, rotation, color expansion, and others. GE 206through a built-in Stretch Block Transfer (STRBLT) function furtherperforms video image expansion, progressive scanning conversion, YcbCr(YUV) to RGB color-space conversion, etc. In short, GE 206 freesprocessing unit 105 from the video/graphics display rendering functionto allow processing unit 105 to perform time-critical or real-timeoperations.

MIU 207 controls all read and write transactions from/to the framebuffer, video buffers, and transactional registers in SRAM (framebuffer) 202. Such read and write requests may come from the host CPU viaCIF 201, GE 206, pixel processing logic 208, FPI 209, etc. In addition,MIU 207 performs tasks associated with memory addressing, memory timingcontrol, and others. Post-processing module 211 removes blocking andringing artifacts from decompressed MPEG video image data to improve thequality of the decompressed video data. The decompressed MPEG videoimage data can be received from, for example, an optical media playervia serial interface 111 or MPEG-4 decoder 212. The filtered video imagedata is then sent to SRAM 202.

Pixel processing logic 208 retrieves video/graphics data from thebuffers in SRAM 202 via MIU 207, serializes the image data into pixels,and formats the pixels into predetermined formats before outputting themto FPI 209 or CRT DAC 210. Accordingly, pixel processing logic 208generates the required horizontal and vertical display timing signals,memory addresses, read requests, and control signals to access imagedata stored in SRAM 202. If the display device involved is a LCD, pixeldata from pixel processing logic 208 is sent to FPI 209 before beingpassed on to the LCD. FPI 209 further processes the data by furtheradding different color hues or gray shades for display. Additionally,depending on whether a thin film transistor (TFT) LCD (a.k.a., activematrix LCD) or a super twisted nematic (STN) LCD (a.k.a., passive matrixLCD) is used, FPI 209 formats the data to suit the type of display.Furthermore, FPI 209 allows color data to be converted into monochromedata in the event a monochrome LCD is used. Conversely, if the displaydevice is a cathode ray tube (CRT), pixel data is provided to CRTdigital-to-analog converter (DAC) 210 prior to being sent to the CRT.CRT DAC 210 converts digital pixel data from pixel processing logic 208to analog Red Green and Blue (RGB) signals to be displayed on the CRTmonitor.

Reference is now made to FIG. 3 illustrating in greater detail exemplaryMPEG-4 video encoder 213 that implements an embodiment of the presentinvention. As shown in FIG. 3, MPEG-4 video encoder 213 includes motioncompensator (−) (MC−) 301, DCT module 302, quantizer 303, memory 304,buffer 305, inverse quantizer 306, Inverse DCT (IDCT) module 307, motioncompensator (+) (MC+) 308, cache 309, motion estimator 310, rate controlmodule 311, alternative coefficient/discrete coefficient (AC/DC) module312, scan module 313, run-length event (RLE) module 314, and variablelength coding (VLC) 315. It is clear that the scope of the presentinvention covers embodiments in which the MPEG-4 video encoder (i.e.,the video encoding function) resides externally and independently ofgraphics/display controller 107.

Video input from a source such as a video camera connected to system 100is provided to memory 304. The video input from the source is thecurrent video frame data. Preferably, memory 304 is separated into acurrent frame area to store data from the current video input, areference frame/reconstructed frames area to store data from thereference video frame and data from a video frame reconstructed fromcompression, and an encoded bitstream buffer to store data from afreshly encoded video frame by encoder 213. Cache 309 fetches currentvideo frame data from memory 304 one macroblock at a time and referencevideo frame data several macroblocks at a time (these severalmacroblocks are adjacent neighbors). Cache 309 receives as input themotion vectors associated with the “good” match video block determinedfrom motion estimator 310. Cache 709 provides data from the currentvideo frame and data from the reference video frame to MC− 301 andmotion estimator 310 based on the motion vectors of the “good” matchvideo block received. Cache 309 also provides data from the referencevideo frame to MC+ 308 based on the motion vectors of the “good” matchvideo block received. Each macroblock typically has six blocks of data(YUV 4:2:0) in which four (Y0-Y3) are luminance data and two (U & V) arechrominance data.

MC− 301 is essentially a subtractor in which prediction data from areference video frame is subtracted from data from a current videoframe, which has been presented in the correct order for encodingaccording to the desired Group Of Pictures (GOP) structure. Thesubtractor is disabled (e.g., the prediction is set to zero) forI-frames or I-macroblocks. The output of MC− 301, which is theprediction error (or the video input in the case of I-frames), is passedto DCT module 302 which performs the Discreet Cosine Transformation(DCT) and outputs DCT coefficients to quantizer 303. The DCTcoefficients generally include a single DC coefficient and a number ofAC coefficients. Some of the AC coefficients are non-zero. While the DCcoefficient represents the average value in the macroblock, the ACcoefficients represent various harmonic frequencies in the macroblock.The DCT coefficients are arranged in a coefficient block that isequivalent in size (8×8) to the pixel block. Quantizer 303 carries outthe quantization process which may be generalized as a step to weightthe DCT coefficients based on the amount of noise that the human eye cantolerate at each spatial frequency so that a reduced set of coefficientscan be generated. This may be generally accomplished by scaling thecoefficient signals using a scalar value Q_(P). This causes some of thesmall coefficients to be divided down and truncated to zero therebyreducing the number of quantization levels available for encoding. Thequantized DCT coefficients are provided to buffer 305 for temporarystorage before they are passed on to AC/DC prediction module 312 andinverse quantizer 306. In the preferred embodiment, buffer 305 is 48rows deep×96 bits wide dual port SRAM with one port dedicated for writeoperations from quantizer 303 and the other port dedicated for readoperations to inverse quantizer 306 and AC/DC predition module 312.

AC is typically defined as a DCT coefficient for which the frequency inone or both dimensions is non-zero (higher frequency). DC is typicallydefined as a DCT coefficient for which the frequency is zero (lowfrequency) in both dimensions. AC/DC prediction module 312, whichimplements the present invention, predicts the AC and DC for the currentblock based on a gradient prediction analysis of the AC and DC values ofadjacent blocks such as an adjacent left top block, a top block, and anadjacent left block. For example, the prediction can be made as follows:

If (|B−A|≧|B−C|)

-   -   then X=A    -   else X=C        where B is the AC or DC value of the left top block relative to        the current block, C is the AC or DC value of the top block        relative to the current block, A is the AC or DC value of the        left block relative to the current block, and X is the AC or DC        value of the current block.

FIG. 4 illustrates a format structure of adjacent DCT coefficient blocksto be processed by AC/DC prediction module 312. As shown, in each DCTcoefficient block, the DC coefficient is situated at the very upper leftcorner and the AC coefficients are provided throughout the remainder ofthe block with the most significant (e.g., nonzero) coefficients beingsituated horizontally in the first row (i.e., the row occupied by the DCcoefficient) or vertically in the first column (i.e., the columnoccupied by the DC coefficient).

Referring now back to FIG. 3, buffer 305 stores the AC and DCcoefficients values of the current macroblocks X and at least the AC andDC coefficient values of adjacent macroblocks A, B, and C relative tothe current macroblock X. Adjacent macroblocks A, B, and C are allprocessed before the current macroblocks so buffer 305 stores thecoefficients of a predetermined number of processed macroblocks receivedover time from quantizer 303. As each new macroblock is processed, thecontent of buffer 504 is updated/reorganized to reflect the appropriateadjacent macroblocks A, B, and C.

In accordance to the present invention, AC/DC prediction module 312 hasthree AC prediction modes: always on, always off, and dynamic on. AC/DCprediction module 312 selects one of three prediction modes andgenerates an AC prediction flag to identify a mode of operation. AC/DCprediction module 312 outputs a DC residual signal, AC signals(representing either AC coefficients or AC residuals), and AC predictionflag.

The order of operation of AC/DC prediction module 312 and quantizer 303in the data path of MPEG encoder 213 is insignificant. It should beclear to a person of ordinary skill in the art that while FIG. 3illustrates quantizer 303 preceding AC/DC prediction module 312 in thedata path, the order of the circuits may be reversed with AC/DCprediction module 312 preceding quantizer 303.

Additional bandwidth efficiency can be achieved by tying a scandirection of VLC module 315 to the gradient prediction. For this reason,AC/DC prediction module 312 provides the AC and DC predictedcoefficients to scan module 313 which forms a 64-elements long vectorfrom the two-dimensional array macroblock such that the low frequency(e.g., DC) components are placed at the beginning of the vector. Thegradient analysis and inter/intra analysis performed in AC/DC predictionmodule 312 is used to select one of three scan directions:Alternate-Horizontal, Alternate-Vertical, and ZigZag (ZZ). Tables 1-3summarizes the order of the three aforementioned scan patterns. Moreparticularly, Tables 1-3 illustrate three 8×8 arrays each having anumber in each array cell indicating the order the content of thecorresponding cell is being accessed by scan module 312 to form the64-elements vector. As a partial illustration of a scan consider forexample Table 1, the Alternate-Horizontal Scan pattern, the scan startsfrom the most upper left cell with the number zero (0), the position ofthe DC residual coefficient of the block. From this cell, the scantraverses three positions in the horizontal direction (i.e., 0-3). Fromthe fourth cell, the scan jumps down to the first cell of the secondrow. From this cell, the Patent scan traverses one position in thehorizontal direction (i.e., 4-5). Next, the scan jumps down to the firstcell of the third row and traverses one position in the horizontaldirection (i.e., 6-7). The scan continues following the same logic in anascending order.

TABLE 1 Alternate-Horizontal Scan Pattern 0 1 2 3 10 11 12 13 4 5 8 9 1716 15 14 6 7 19 18 26 27 28 29 20 21 24 25 30 31 32 33 22 23 34 35 42 4344 45 36 37 40 41 46 47 48 49 38 39 50 51 56 57 58 59 52 53 54 55 60 6162 63

TABLE 2 Alternate-Vertical Scan Pattern 0 4 6 20 22 36 38 52 1 5 7 21 2337 39 53 2 8 19 24 34 40 50 54 3 9 18 25 35 41 51 55 10 17 26 30 42 4656 60 11 16 27 31 43 47 57 61 12 15 28 32 44 48 58 62 13 14 29 33 45 4959 63

TABLE 3 ZigZag Scan Pattern 0 1 5 6 14 15 27 28 2 4 7 13 16 26 29 42 3 812 17 25 30 41 43 9 11 18 24 31 40 44 53 10 19 23 32 39 45 52 54 20 2233 38 46 51 55 60 21 34 37 47 50 56 59 61 35 36 48 49 57 58 62 63

Scan module 313 provides the 64-elements vector to RLE module 314 togenerate run-level events. In general, RLE module 314 determines thenumber of consecutive zeros in the vector and forms RLE acceptable wordsbased on the determination. After quantization, there are likely asignificant number of zeros (likely to be the high frequency components)in the block and there is no need to transmit or store such information.Accordingly, a RLE word represents the number of zeros betweenconsecutive non-zero elements in the vector. The RLE word also includesthe value of the last non-zero element after the zeros and informationindicating whether this value is the very last component in the vector.

The RLE words are provided to VLC module 315 which maps RLE words intoVLC patterns. For example, certain RLE words are given specific bitpattern. The most common RLE words are given the shortest VLC bitpattern. VLC patterns are specified in MPEG-4 standard. (See “MPEG-4Information Technology-Coding of Audio-Visual Objects-Part 2: Visual”ISO/IEC/14496-2:1999). Run-length and variable-length coding (thecombination coding) are commonly referred to as Huffman coding) and canbe combined into one VLC module. In general, due to the non-uniformdistribution of the DCT coefficients wherein most of the non-zero DCTcoefficients of an image tend to be located in a general area, VLC andrun-length encoding are used to exploit this distribution characteristicto identify non-zero DCT coefficients from zero DCT coefficients. In sodoing, redundant/predictable information can be removed. The encoded(i.e., compressed) block of video frame data is then sent to memory 304for storing in the encoded frame cache.

The process of motion compensated prediction requires a signal on whichto base the prediction. This signal represents the reference/previousvideo frame data which is stored in the reference cache of memory 304.To ensure that the prediction process in MPEG-4 video encoder 213 basesits prediction on a signal that is substantially similar to thatavailable in MPEG-4 video decoder 212 (i.e., a remote video decoder), alocal decoder is included in video encoder 213 to generate a locallydecoded signal in the encoder. The local decoder, which consists ofinverse quantizer 306, IDCT 307, and MC+ 308, basically undoes theencoding stages of quantizer 303 and DCT 302 to produce a decodedprediction error and adds it back into a suitably delayed version of theprediction (reference frame) data to produce a locally decoded(reconstructed) signal with motion compensation. The delayed predictiondata is provided by cache 309.

The reconstructed signal is sent to the reconstruction cache of memory304 for storage. For each macroblock in the current video frame, motionestimator 310, which implements the present invention, searches for a“good” matched macroblock in the reference video frame based on aminimum SAD value. Motion estimator 310 receives as input blocks ofcurrent frame and reference frame data. Motion estimator 310 alsoreceives a signal indicating the frame type from rate control module311. Motion estimator 310 also determines the motion vector. Motionestimator 310 further determines whether a macroblock in the currentvideo frame is intra (encoded independently) or inter (encoded aftermotion compensation). These determinations are communicated to ratecontrol module 311 and AC/DC prediction module 312. The motion vectordeterminations are communicated to cache 309 and MC+ 308.

The rate of the bitstream output by VLC module 315 may fluctuate overtime depending on the content of the video data (i.e., changing scenesand objects). This variable bit rate may be undesirable at times.Instead, a constant bit rate may be desirable to fit the availablechannel or in the case of statistical multiplexing so that a constantbit rate can be shared between several video signals. Hence, dependingon the application, either variable bit rate or constant bit rate isselected. It is then important to ensure that the average bit-rate ofthe buffer input is the same as that of the channel and neither bufferoverflows or underflows. Rate control module 311 is used to control theaverage bit rate at the bitstream buffer in memory 304 to stay inside anacceptable limit range to prevent overflow and underflow. To achieve theaverage bit rate control, rate control module 311 varies thequantization factors in quantizer 303 and AC/DC module 312. Whilecoarser scale generates a lower average bit rate, at the expense ofpicture quality, a finer scale produces better pictures but at a higheraverage bit rate. As the buffer fills, quantizer 303 and AC/DC module312 get coarser, which tends to reduce the average bit rate, helping thebuffer to empty. Additionally, rate control module 311 takes intoconsideration the expected differences (e.g., through modelingprojection) in bit rates generated by I and P frames.

Referring to FIG. 5 illustrating a block diagram of the relevantcomponents of an exemplary embodiment of AC/DC prediction module 312which implements the present invention. As shown in FIG. 5, AC/DCprediction module 312 comprises DC predictor 501, AC predictor 502,subtractor/adder 503, decision logic 504, subtractor/adder 505, overflowcalculator 506, latch circuits 507-510, program register 511, andinverters 513-514.

Decision logic 507 receives as inputs inter/intra signal from motionestimator 210, AC on/off/dynamic signal from an external programregister (not shown) that is programmed by the CPU, and AC predictionflag from overflow calculator 506. In response, decision logic 507outputs zz signal to program register 511, inter enable signal tolatches 507 and 509, intra & AC-off enable signal to latch circuits 508and 510, DC predictor enable signal to DC predictor 501, and ACpredictor enable signal to AC predictor 502. By providing AC predictionflag signal and AC predictor enable signal as inputs to an AND-gate andAC prediction flag signal and AC predictor enable signal as inputs toanother AND-gate, when AC prediction flag signal is deasserted, itoverrides AC predictor enable signal and intra & AC off enable signal toessentially reverse the effect of their states (e.g., from low to highor from high to low). When AC prediction flag is asserted, the effect ofthe states of AC predictor enable signal and intra & AC off enablesignal are maintained.

If decision logic 504 receives inter/intra input signal indicating thatthe current macroblock is inter, decision logic 504 asserts inter enablesignal, asserts intra & AC off enable signal, asserts ZZ signal,deasserts DC predictor enable signal, and deasserts AC predictor enablesignal. When asserted, ZZ signal sets the MSB in program register 511 tohigh. When asserted, inter enable signal disables latch circuit 507because inter enable signal is provided to inverter 514 prior toreaching latch circuit 507, respectively. Conversely, when asserted,inter enable signal enables latch circuit 509. When asserted, intra &AC-off enable signal disables latch circuit 508 because intra & AC-offenable signal is provided to inverter 513 prior to reaching latchcircuit 508. Conversely, when asserted, inter enable signal enableslatch circuit 509 and intra & AC-off enables signal enables latchcircuit 510. When deasserted, DC predictor enable signal disables DCpredictor 501 and AC predictor enable signal disables AC predictor 502.In so doing, DC predictor 501 and AC predictor 502 are disabled and theDC and AC coefficients from buffer 305 which are provided as inputs tolatch circuits 509 and 510, respectively, are provided as outputs oflatch circuits 509 and 510 to scan module 313 which is commanded by theMSB of program register 511 to perform a ZZ scan. The AC and DCcoefficients are provided to a current data packet in the data partitionmode.

If inter/intra input signal indicates the current macroblock is intraand AC on/off/dynamic signal indicates that the selected AC mode is off,decision logic 504 asserts intra & AC off enable signal, deasserts interenable signal, deasserts AC predictor enable signal, asserts DCpredictor enable signal, deasserts AC predictor enable signal, andasserts ZZ signal which sets the MSB in program register 511 to high.When asserted, intra & AC-off enable signal disables latch circuit 508via inverter 513 while enables latch circuit 510. When deasserted, interenable signal disables latch circuit 509 while enables latch circuit 507via inverter 514. The deasserted AC predictor enable signal disables ACpredictor 502. The asserted DC predictor enable signal enables DCpredictor 501. In so doing, DC prediction is performed, AC prediction isdisabled, the AC coefficients from buffer 305, which are provided asinputs to latch circuit 510, are provided as outputs of latch circuit510 to scan module 313, and the DC predict coefficient (residual signal)from subtractor 503 is provided as output of latch circuit 507 to scanmodule 313. Scan module 313 is commanded by the MSB of program register511 to perform a ZZ scan. The AC coefficients and DC predictcoefficients are provided to a current data packet in the data partitionmode.

If inter/intra input signal indicates the current macroblock is intraand AC on/off/dynamic signal indicates that the selected AC mode is on,decision logic 504 deasserts intra & AC-off enable signal, deassertsinter enable signal, asserts AC predictor enable signal, asserts DCpredictor signal, and deasserts ZZ signal to set the MSB in programregister 511 to low. When the MSB of program register is low, then itsLSB is used to determine whether the scan direction is horizontal orvertical. When deasserted, intra & AC-off enable signal disables latchcircuit 510 while enables latch circuit 508 via inverter 513. Whendeasserted, inter enable signal disables latch circuit 509 while enableslatch circuit 507. The asserted DC predictor enable signal and assertedAC predictor enable signal enables DC predictor 501 and AC predictor502, respectively. In so doing, DC prediction is performed, ACprediction is performed, the AC predict coefficients (residual signal)from subtractor 505 is provided as output of latch circuit 508 to scanmodule 313, and the DC predict coefficient (residual signal) fromsubtractor 503 is provided as output of latch circuit 507 to scan module313. With the MSB of program register 511 set to low, scan module 313 iscommanded by the LSB of program register 511 which is programmed by thevalue of the hor/vert signal generated by DC predictor 501. As anexample, if the LSB of program register 511 is high, the scan module 313performs an alternate-horizontal scan. If the LSB of program register511 is low, the scan module 313 performs an alternate vertical scan. TheAC coefficients and DC predict coefficients are provided to a currentdata packet in the data partition mode.

If inter/intra input signal indicates the current macroblock is intraand AC on/off/dynamic signal indicates that the selected AC mode isdynamic, decision logic 507 deasserts intra & AC-off enable signal,deasserts inter enable signal, asserts AC predictor enable signal,asserts DC predictor enable signal, and deasserts ZZ signal to set theMSB in program register 511 to low. In so doing, DC prediction isenabled, AC prediction is enabled, the AC predict coefficients (residualsignal) from subtractor 505 is provided as output of latch circuit 508to scan module 313, and the DC predict coefficients (residual signal)from subtractor 503 is provided as output of latch circuit 507 to scanmodule 313. This represents the first pass for the AC prediction dynamicmode. With the MSB of program register 511 set to low, scan module 313is commanded by the LSB of program register 511 which is programmed bythe value of the hor/vert signal generated by DC predictor 501. As anexample, if the LSB of program register 511 is high, the scan module 313performs an alternate-horizontal scan. If the the LSB of programregister 511 is low, the scan module 313 performs an alternate verticalscan.

In view of the functions and description related to decision logic 504as well as other information provided in the detailed descriptionsection, a person of ordinary skill in the art should be able to easilydesign a decision logic that performs the functions described.

In accordance to the present invention, during the second pass of the ACdynamic mode, overflow calculator 506 determines whether the currentpacket has exceeded the maximum packet size under the present selecteddata partition mode (e.g., 1024 bits, 2048 bits, or 4096 bits). If themaximum packet size selected is not exceeded if the current macroblockis added to the current packet, overflow calculator 506 asserts ACprediction flag signal which is provided to RLE 314 and to AC predictor502 to so signify. When asserted, AC prediction flag further indicatesto AC predictor 502 that AC prediction is to continue. Otherwise,overflow calculator 506 deasserts AC prediction flag signal to signifyto RLE 314 that the current macroblock is added to the next packet andthat AC prediction is to be disabled. Hence, AC prediction flag signaloverrides AC predictor enable signal as well as Intra & AC off enablesignal from decision logic 504. Overflow calculator 506 determines thatan overflow condition occurs according to the following equation:

(Nonzero#−DCnonzero#)*31+128+BitsInPacket>PacketSize

wherein Nonzero# is the number of nonzero AC coefficients determined bythe AC prediction process, DCnonzero# is the number of nonzero DCcoefficients determined by the DC prediction process, 31 is the maximumsize for a nonzero coefficient, 128 is the maximum bits for part 1 andpart 2 of a macroblock processed in data partition mode, BitsInPacket isthe number of bits currently in the packet until the previousmacroblock, and PacketSize is the preset packet size for the datapartition mode.

Overflow calculator 506 receives as inputs Nonzero# signal from ACpredictor 502 after AC prediction is carried out for the entire currentmacroblock, DCnonzero# signal from DC predictor 501 after DC predictionis carried out for the entire current macroblock, BitsInPacket signalfrom VLC 315, and PacketSize signal from CPU 205. It should be clear toa person of ordinary skill in the art that overflow calculator 506 canbe made part of decision logic 504.

In summary, if an overflow condition is detected in the second pass ofAC prediction dynamic mode, AC prediction is then disabled and the ACcoefficients provided by buffer 305 and the DC predict residual signalare provided to scan module 313 and then to RLE module 314 via latchcircuits 510 and 507, respectively. With AC prediction flag deassertedindicating the overflow condition, RLE module 314 put the DC predictsignal and the AC coefficients of the present macroblock into the nextpacket. No prediction for AC coefficient is performed in this casebecause as the first macroblock in the new packet, it has littlecorrelation with previous macroblocks. No prediction means nounnecessary lossy compression and no degraded video quality. If nooverflow condition is detected, the AC predict residual and DC predictresidual signals are provided to scan module 313 and then to RLE module314 via latch circuits 508 and 507, respectively. Hence, in accordancewith the present invention, AC prediction is dynamically performed tooptimize compression efficiency while maintaining video quality by notimplementing unnecessary compression.

DC predictor 501 and AC predictor 502 perform gradient analyses. DCpredictor 501 compares DC_(A), a DC coefficient of block A (see FIG. 4for an illustration of the position of blocks A, B, C, and X), with aDC_(B), a DC coefficient of block B, to determine the vertical gradient.DC predictor 501 also compares DC_(C), a DC coefficient of block C, withDC_(B), the DC coefficient of block B to determine the horizontalgradient. The vertical and horizontal gradients are compared to eachother with the greater gradient relative to block B to be used as abasis of prediction. This is because block B is the farthest blockrelative to the current block X and the greater gradient relative toblock B is indicative that the involved adjacent block (A or C) relativeto the current block X likely has a higher correlation with the currentblock.

If the vertical gradient is greater than the horizontal gradient, blockA will likely have high correlation with block X and DC predictor 501employs horizontal prediction which uses block A as the basis forprediction of block X. Conversely, if the horizontal gradient is greaterthan the vertical gradient, block C will likely have high correlationwith block X and DC predictor 501 employs vertical prediction which usesblock C as the basis for prediction of block X. DC predictor 501generates hor/vert signal based on whether horizontal or verticalprediction is used. DC predictor 501 provides the DC coefficient of theblock used for prediction to subtractor/adder 503 which subtracts/addsthe DC coefficient output by DC predictor 501 from/to the DC coefficientof block X to obtain the DC predict coefficient (residual signal) forblock X. Before sending the DC coefficient of the block used forprediction to subtractor/adder 503, DC predictor 501 performs an integerdivision operation on the DC coefficient using a DC_scaler which isbased on the quantization step size Q_(P) used in the quantizationprocess of the relevant block. In an alternate embodiment, DC predictor501 and subtractor/adder 503 can be combined into one circuit. Table 4below summarizes, as an example, the DC_Scaler values for differentcomponent types and step sizes Q_(P). Hence, DC predictor 501 combinedtogether with subtractor/adder 503 perform the following:

If (predict from block C)

QF _(X) =PQF _(X) +F _(C) //DC_scaler

Else (if predict from block A)

QF _(X) =PQF _(X) +F _(A) //DC_scaler

where QF_(X) is the DC predict coefficient (residual signal), PQF_(X) isthe DC coefficient of the current block X, F_(C) and F_(A) are the DCcoefficients of blocks C and A, respectively.

TABLE 4 DC_Scaler Values Component: Type Q_(P) = 1-to-4 Q_(P) = 5-to-8Q_(P) = 9-to-24 Q_(P) ≧ 25 Luminance: 8 2*Q_(P) Q_(P) + 8 2*Q_(P) − 16Type1 Chrominance: 8 (Q_(P) + 13)/2 (Q_(P) + 13)/2 Q_(P) − 6 Type2

AC predictor 502 and subtractor/adder 505 utilize a substantiallysimilar scheme to generate AC predict residual signal. In an alternateembodiment, AC predictor 502 and subtractor/adder 504 can be combinedinto one circuit. AC predictor 502 utilizes hor/vert signal generated byDC predictor 501 to determine whether a horizontal prediction (i.e., inwhich block A is used as basis for AC prediction for current block X) orvertical prediction (i.e., in which block C is used as basis for ACprediction for current block X) is employed. The AC coefficients from aDCT transform that may exhibit the highest correlation between blocksare those in the same first row or the same first column as the DCcoefficient. If horizontal prediction is used, the AC coefficients fromthe same column as the DC coefficient in block A are used. Accordingly,for each AC coefficient of block X in the same column as the DCcoefficient (i.e., AC_(X)(0,1) through AC_(X)(0,n)), AC predictor 502performs a prediction corresponding to the similarly located ACcoefficient from block A (i.e., AC_(A)(0,1) through AC_(A)(0,n)). Ifvertical prediction is used, the AC coefficients from the same row asthe DC coefficient in block C are used. Accordingly, for each ACcoefficient of block X in the same row as the DC coefficient (i.e.,AC_(X)(1,0) through AC_(X)(n,0)), AC predictor 502 performs a predictioncorresponding to the similarly located AC coefficient from block C(i.e., AC_(C)(0,1) through AC_(C)(0,n)).

AC predictor 502 provides the AC coefficients of the block used forprediction to subtractor 505 which subtracts/adds the AC coefficientsoutput by AC predictor 502 from/to the AC coefficients of block X toobtain the AC predict coefficient (residual signal) for block X. Beforesending the AC coefficient of the block used for prediction tosubtractor/adder 505, AC predictor 502 performs a integer scalingoperation on the AC coefficients using the ratio between thequantization step size Q_(P) of the relevant adjacent block A or C(based on prediction direction) and the quantization step size Q_(PX) ofpresent block X. This compensates for the differences in thequantization of previous horizontally adjacent or vertically adjacentblocks used in AC prediction Hence, AC predictor 502 combined togetherwith subtractor/adder 505 perform the following:

If (predict from block C)

QF _(X) [j][0]=PQF _(X) [j][0]+(QF _(C) [j][0]*QP _(C))//QP _(X)

Else (if predict from block A)

QF _(X)[0][i]=PQF _(X)[0][i]+(QF _(A)[0][i]*QP _(A))//QP _(X)

where i=1 to 7, j=1 to 7, QF_(X)[i][j] is the AC predict coefficient(residual signal) from the X block, QF_(A)[i][j] is the AC coefficientfrom the A block, QF_(C)[i][j] is the AC coefficient from the C block,PQF_(X)[i][j] is the AC coefficient of the current block X, and QP_(A),QP_(C), & QP_(X) are the quantization step sizes associated with blocksA, C, and X, respectively.

In the present embodiment, latch circuits 507 and 509 each consists ofsix D-type flip flops connected together which are designed toaccommodate the total six DC coefficients of the six blocks Y0, Y1, Y2,Y3, U, and V (i.e., one DC coefficient per block) in a macroblock. Othertypes of flip flops can also be used. Latch circuits 508 and 510 eachconsists of forty-two D-type flip flops connected together which aredesigned to accommodated the total forty-two AC coefficients of the sixblocks Y0, Y1, Y2, Y3, U, and V (i.e., seven AC coefficients per block)in a macroblock. Latch circuits 507-508 are designed to store all the ACand DC predict residual signals following the prediction process for allsix blocks in the macroblock before outputting them.

The operation of AC/DC prediction module 312 as described above may alsobe performed in software using a programmed processor or digital signalprocessor. FIG. 6 is a flow chart illustrating an embodiment of thedynamic AC prediction method in accordance to the present invention. Instep 600, a determination is made whether the current macroblock isinter or intra. If the current macroblock is inter, a zz scan isperformed (step 605) and the ZZ scanned AC and DC coefficients are sentto RLE module 314 (step 610). If the current macroblock is intra, it isdetermined whether the AC prediction mode is OFF (step 615). If the ACprediction mode is OFF, DC prediction is performed (step 620) and zzscan is performed (step 625). The scanned AC coefficients and the DCpredict residual coefficients are sent to RLE module 314 (step 630). Ifthe AC prediction mode is not OFF, it is determined whether the ACprediction mode is ON (step 635).

If the AC prediction mode is ON, DC & AC prediction are performed (step665), predict direction (hor/vert) is determined (step 670), DC_Scalervalue is determined (step 675). The order of these three steps maychanged. Next, it is determined whether the predict direction ishorizontal (step 680). If yes, an alternate-vertical scan is performed(step 685) and the scanned AC & DC predict residuals are sent to the RLE(step 695). If not, an alternate-horizontal scan is performed (step 690)and the scanned AC & DC predict residuals are sent to the RLE (step695).

If the AC prediction mode is not ON, a determination is made whether theAC prediction mode is Dynamic (step 640). If the AC prediction mode isDynamic, DC & AC prediction are performed (step 645), predict direction(hor/vert) is determined (step 650), DC_Scaler value is determined (step655). The order of these three steps may changed. Next, it is determinedwhether, with the current macroblock, the current packet exceeds themaximum preset limit (step 660). If yes, steps 620-630, which arediscussed earlier, are carried out. If not, it is determined whether thepredict direction is horizontal (step 680). If yes, analternate-vertical scan is performed (step 685) and the scanned AC & DCpredict residuals are sent to the RLE (step 695). If not, analternate-horizontal scan is performed (step 690) and the scanned AC &DC predict residuals are sent to the RLE (step 695).

A couple embodiments of the present invention, a method and apparatus toprevent video packet overflow in a MPEG data partition mode whileminimizing the compression efficiency impact and maintaining the videoquality, are presented. While the present invention has been describedin particular embodiments, the present invention should not be construedas limited by such embodiments, but rather construed according to thebelow claims.

1. An apparatus for performing dynamic AC prediction, said apparatuscomprising: a DC prediction component for performing DC prediction for acurrent macroblock using DC coefficients associated with at least oneadjacent macroblock; an AC prediction component for performing ACprediction for said current macroblock using AC coefficients associatedwith said at least one adjacent macroblock; and a decision logic coupledto said DC prediction component and said AC prediction component, saiddecision logic for determining whether an overflow condition is to occurin a current data packet if said current macroblock is encoded in saidcurrent data packet, said decision logic further for, if no overflowcondition is to occur, supplying AC predict coefficients and DC predictcoefficients for encoding said current macroblock in said current datapacket.
 2. The apparatus of claim 1, wherein said decision logic isfurther operable to, if said overflow condition is to occur, supply saidAC coefficients and said DC predict coefficients for encoding saidcurrent macroblock in a new data packet.
 3. The apparatus of claim 1,wherein said decision logic is further operable to determine whethersaid overflow condition is to occur in said current packet prior to saidAC prediction component performing further AC prediction for saidcurrent macroblock.
 4. The apparatus of claim 1, wherein said decisionlogic is further operable to control said DC prediction component toperform a second DC prediction for said current macroblock if saidoverflow condition is to occur, and wherein said decision logic isfurther operable to control said AC prediction component to suspendfurther AC prediction for said current macroblock if said overflowcondition is to occur.
 5. The apparatus of claim 1, wherein said DCprediction of said DC prediction component, said AC prediction of saidAC prediction component, and said determining whether an overflowcondition is to occur by said decision logic are performed in a datapartition mode.
 6. The apparatus of claim 1, wherein said decision logicis further operable to, if no overflow condition is to occur, determinea predict direction associated with said DC prediction and said ACprediction, wherein said decision logic is further operable to, if saidpredict direction is determined to be horizontal, generate a signal forperforming an alternate-horizontal scan, and wherein said decision logicis further operable to, if said predict direction is determined to bevertical, generate a signal for performing an alternate-vertical scan.7. The apparatus of claim 1, wherein said decision logic is furtheroperable to, if said overflow condition is to occur, generate a signalfor performing a zig-zag scan.
 8. The apparatus of claim 1, wherein saidDC coefficients and said AC coefficients comprise a transformcoefficient data set, wherein said transform coefficient data set isaccessed from a buffer coupled to said apparatus, and wherein saidtransform coefficient data set is generated using a discrete cosinetransform prior to storage in said buffer.
 9. The apparatus of claim 1,wherein said decision logic is further operable to, before determiningwhether said overflow condition is to occur, determine a macroblock typeof said current macroblock, wherein said decision logic is furtheroperable to, if said current macroblock comprises an inter block, supplysaid AC coefficients and said DC coefficients for encoding said currentmacroblock in said current data packet, wherein said decision logic isfurther operable to, if said current macroblock comprises an intrablock, determine an AC prediction mode status associated with said ACprediction, wherein said decision logic is further operable to, if saidAC prediction is disabled, supply said AC coefficients and said DCpredict coefficients for encoding said current macroblock in saidcurrent data packet, and wherein said decision logic is further operableto, if said AC prediction is enabled, supply said AC predictcoefficients and said DC predict coefficients for encoding said currentmacroblock in said current data packet.
 10. An apparatus for performingdynamic AC prediction, said apparatus comprising: an AC predictioncomponent for performing AC prediction for said current macroblock usingAC coefficients associated with said at least one adjacent macroblock;and a decision logic coupled to said AC prediction component, saiddecision logic for determining whether an overflow condition is to occurin a current data packet if said current macroblock is encoded in saidcurrent data packet, said decision logic further for, if no overflowcondition is to occur, maintaining said AC prediction in an enabledstate and designating said current macroblock for encoding in saidcurrent data packet, and said decision logic further for, if saidoverflow condition is to occur, suspending said AC prediction anddesignating said current macroblock for encoding in a new data packet.11. The apparatus of claim 10 further comprising: a DC predictioncomponent coupled to said decision logic and for performing DCprediction for a current macroblock using DC coefficients associatedwith at least one adjacent macroblock, wherein said decision logic isfurther operable to, before determining whether said overflow conditionis to occur, determine a macroblock type of said current macroblock,wherein said decision logic is further operable to, if said currentmacroblock comprises an inter block, supply said AC coefficients andsaid DC coefficients for encoding said current macroblock in saidcurrent data packet, wherein said decision logic is further operable to,if said current macroblock comprises an intra block, determine an ACprediction mode status associated with said AC prediction, wherein saiddecision logic is further operable to, if said AC prediction isdisabled, supply said AC coefficients and said DC predict coefficientsfor encoding said current macroblock in said current data packet, andwherein said decision logic is further operable to, if said ACprediction is enabled, supply said AC predict coefficients and said DCpredict coefficients for encoding said current macroblock in saidcurrent data packet.
 12. The apparatus of claim 11, wherein saiddecision logic is further operable to, if said overflow condition is tooccur, control said performing a second DC prediction for said currentmacroblock.
 13. The apparatus of claim 10, wherein said decision logicis further operable to, if no overflow condition is to occur, supply ACpredict coefficients for encoding said current macroblock in saidcurrent data packet, and wherein said decision logic is further operableto, if said overflow condition is to occur, supply said AC coefficientsfor encoding said current macroblock in a new data packet.
 14. Theapparatus of claim 10, wherein said decision logic is further operableto determine whether said overflow condition is to occur in said currentpacket prior to said AC prediction component performing further ACprediction for said current macroblock.
 15. The apparatus of claim 10,wherein said decision logic is further operable to, if no overflowcondition is to occur, determine a predict direction associated withsaid AC prediction, wherein said decision logic is further operable to,if said predict direction is determined to be horizontal, generate asignal for performing an alternate-horizontal scan, and wherein saiddecision logic is further operable to, if said predict direction isdetermined to be vertical, generate a signal for performing analternate-vertical scan.
 16. The apparatus of claim 10, wherein saiddecision logic is further operable to, if said overflow condition is tooccur, generate a signal for performing a zig-zag scan.
 17. An apparatusfor performing dynamic AC prediction, said apparatus comprising: an ACprediction component for performing AC prediction for said currentmacroblock using AC coefficients associated with said at least oneadjacent macroblock; a DC prediction component for performing DCprediction for a current macroblock using DC coefficients associatedwith at least one adjacent macroblock; an overflow component forcomparing a predetermined packet size and a size of a current datapacket with said current macroblock, said overflow component further forgenerating a signal indicating whether an overflow condition is to occurbased upon a result of said comparison; and a decision logic coupled tosaid AC prediction component, said DC prediction component, and saidoverflow component, said decision logic for accessing said signal fromsaid overflow component and determining whether said overflow conditionis to occur in a current data packet if said current macroblock isencoded in said current data packet, said decision logic further for, ifno overflow condition is to occur, maintaining said AC prediction in anenabled state and designating said current macroblock for encoding insaid current data packet.
 18. The apparatus of claim 17, wherein saiddecision logic is further operable to, if said overflow condition is tooccur, suspend said AC prediction and designating said currentmacroblock for encoding in a new data packet.
 19. The apparatus of claim17, wherein said decision logic is further operable to, beforedetermining whether said overflow condition is to occur, determine amacroblock type of said current macroblock, wherein said decision logicis further operable to, if said current macroblock comprises an interblock, supply said AC coefficients and said DC coefficients to avariable-length coding module for encoding said current macroblock insaid current data packet, wherein said decision logic is furtheroperable to, if said current macroblock comprises an intra block,determine an AC prediction mode status associated with said ACprediction, wherein said decision logic is further operable to, if saidAC prediction is disabled, supply said AC coefficients and said DCpredict coefficients to said variable-length coding module for encodingsaid current macroblock in said current data packet, wherein saiddecision logic is further operable to, if said AC prediction is enabled,supply said AC predict coefficients and said DC predict coefficients tosaid variable-length coding module for encoding said current macroblockin said current data packet, and wherein said decision logic is furtheroperable to, if said overflow condition is to occur, control saidperforming a second DC prediction for said current macroblock.
 20. Theapparatus of claim 17, wherein said decision logic is further operableto, if no overflow condition is to occur, supply AC predict coefficientsand DC predict coefficients to said variable-length coding module forencoding said current macroblock in said current data packet, andwherein said decision logic is further operable to, if said overflowcondition is to occur, supply said AC coefficients and said DC predictcoefficients to a variable-length coding module for encoding saidcurrent macroblock in a new data packet.
 21. The apparatus of claim 17,wherein said decision logic is further operable to determine whethersaid overflow condition is to occur in said current packet prior to saidAC prediction component performing further AC prediction for saidcurrent macroblock.
 22. The apparatus of claim 17, wherein said decisionlogic is further operable to, if no overflow condition is to occur,determine a predict direction associated with said AC prediction andsaid DC prediction, wherein said decision logic is further operable to,if said predict direction is determined to be horizontal, generate asignal for performing an alternate-horizontal scan, and wherein saiddecision logic is further operable to, if said predict direction isdetermined to be vertical, generate a signal for performing analternate-vertical scan.
 23. The apparatus of claim 17, wherein saiddecision logic is further operable to, if said overflow condition is tooccur, generate a signal for performing a zig-zag scan.